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Espressif Systems /ESP32-P4 /LP_SYS /INT_CLR

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Interpret as INT_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LP_ADDRHOLE_INT_CLR)LP_ADDRHOLE_INT_CLR 0 (IDBUS_ADDRHOLE_INT_CLR)IDBUS_ADDRHOLE_INT_CLR 0 (LP_CORE_AHB_TIMEOUT_INT_CLR)LP_CORE_AHB_TIMEOUT_INT_CLR 0 (LP_CORE_IBUS_TIMEOUT_INT_CLR)LP_CORE_IBUS_TIMEOUT_INT_CLR 0 (LP_CORE_DBUS_TIMEOUT_INT_CLR)LP_CORE_DBUS_TIMEOUT_INT_CLR 0 (ETM_TASK_ULP_INT_CLR)ETM_TASK_ULP_INT_CLR 0 (SLOW_CLK_TICK_INT_CLR)SLOW_CLK_TICK_INT_CLR

Description

interrupt clear register

Fields

LP_ADDRHOLE_INT_CLR

write 1 to clear lp addrhole int
IDBUS_ADDRHOLE_INT_CLR

write 1 to clear idbus addrhole int
LP_CORE_AHB_TIMEOUT_INT_CLR

Write 1 to clear lp_core_ahb_timeout int
LP_CORE_IBUS_TIMEOUT_INT_CLR

Write 1 to clear lp_core_ibus_timeout int
LP_CORE_DBUS_TIMEOUT_INT_CLR

Write 1 to clear lp_core_dbus_timeout int
ETM_TASK_ULP_INT_CLR

Write 1 to clear etm tasl ulp int
SLOW_CLK_TICK_INT_CLR

Write 1 to clear slow_clk_tick int

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data